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| To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-10167-3E MEMORY CMOS 2 M x 8 BIT FAST PAGE MODE DYNAMIC RAM MB8117800A-60/-70 CMOS 2,097,152 x 8 Bit Fast Page Mode Dynamic RAM s DESCRIPTION The Fujitsu MB8117800A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory cells accessible in 8-bit increments. The MB8117800A features a "fast page" mode of operation whereby highspeed random access of up to 1,024-bits of data within the same row can be selected. The MB8117800A DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby current of the MB8117800A is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. The MB8117800A is fabricated using silicon gate CMOS and Fujitsu's advanced four-layer polysilicon and twolayer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for the MB8117800A are not critical and all inputs are TTL compatible. s PRODUCT LINE & FEATURES Parameter RAS Access Time Random Cycle Time Address Access Time CAS Access Time Hyper Page Mode Cycle Time Low Power Dissipation * * * * * * Operating Current Standby Current MB8117800A-60 60 ns max. 110 ns min. 30 ns max. 15 ns max. 40 ns min. 715 mW max. MB8117800A-70 70 ns max. 130 ns min. 35 ns max. 17 ns max. 45 ns min. 660 mW max. 11 mW max. (TTL level) / 5.5 mW max. (CMOS level) * RAS-only, CAS-before-RAS, or Hidden Refresh * Fast Page Mode, Read-Modify-Write capability * On chip substrate bias generator for high performance 2,097,152 words x 8 bit organization Silicon gate, CMOS, Advanced Capacitor Cell All input and output are TTL compatible 2048 refresh cycles every 32.8ms Self refresh function Early write or OE controlled write capability 1 To Top / Lineup / Index MB8117800A-60/-70 s PACKAGE 28-pin plastic SOJ 28-pin plastic TSOP (II) (LCC-28P-M07) (FPT-28P-M14) (Normal Bend) Package and Ordering Information - 28-pin plastic (400mil) SOJ, order as MB8117800A-xxPJ - 28-pin plastic (400mil) TSOP-II with normal bend leads, order as MB8117800A-xxPFTN 2 To Top / Lineup / Index MB8117800A-60/-70 s PIN ASSIGNMENTS AND DESCRIPTIONS 26-Pin SOJ (TOP VIEW) Designator A0 to A10 Function Address inputs row : A0 to A10 column : A0 to A9 refresh : A0 to A10 Row address strobe Column address strobe Write enable Output enable Data Input/Output +5.0 volt power supply Circuit ground No Connection RAS CAS WE OE DQ1 to DQ8 VCC VSS N.C. 28-Pin TSOP (II) (TOP VIEW) 3 To Top / Lineup / Index MB8117800A-60/-70 s BLOCK DIAGRAM Fig. 1 - MB8117800A DYNAMIC RAM - BLOCK DIAGRAM RAS CAS Clock Gen #1 Write Clock Gen WE Mode Control Clock Gen #2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Row Decoder 16,777,216 Bit Storage Cell Address Buffer & PreDecoder Column Decoder Sense Ampl & I/O Gate Data In Buffer DQ1 to DQ8 Data Out Buffer OE A10 Refresh Address Counter Substrate Bias Gen VCC VSS 4 To Top / Lineup / Index MB8117800A-60/-70 s FUNCTIONAL TRUTH TABLE Operation Mode Standby Read Cycle Write Cycle (Early Write) Read-ModifyWrite Cycle RAS-only Refresh Cycle CAS-beforeRAS Refresh Cycle Hidden Refresh Cycle Clock Input RAS H L L L L L HL CAS H L L L H L L WE X H L OE X L X Address Row -- Valid Valid Valid Valid -- -- Column -- Valid Valid Valid -- -- -- Input Data Input -- -- Valid Valid -- -- -- Output High-Z Valid High-Z Valid High-Z High-Z Valid Refresh -- Yes* Yes* Yes* Yes Yes Yes tCSR tCSR (min) Previous data is kept. tRCS tRCS (min) tWCS tWCS (min) Note HL LH X X HX X X L X; "H" or "L" *; It is impossible in Fast Page Mode. s FUNCTIONAL OPERATION ADDRESS INPUTS Twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix. Since only eleven address bits (A0 to A10) are available, the row and column inputs are separately strobed by RAS and CAS as shown in Figure 1. First, eleven row address bits are input on pins A0-through-A10 and latched with the row address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is automatically treated as the column address. WRITE ENABLE The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored. DATA INPUTS Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data (DQ1-DQ8) is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. 5 To Top / Lineup / Index MB8117800A-60/-70 DATA OUTPUTS The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: tRAC : tCAC : tAA : tOEA : from the falling edge of RAS when tRCD (max) is satisfied. from the falling edge of CAS when tRCD is greater than tRCD (max). from column address input when tRAD is greater than tRAD (max). from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA. The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. FAST PAGE MODE OF OPERATION The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast page of memory, any of 1,024 x 8-bits can be accessed and, when multiple MB8117800As are used, CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. 6 To Top / Lineup / Index MB8117800A-60/-70 s ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Voltage at any pin relative to VSS Voltage of VCC supply relative to VSS Power Dissipation Short Circuit Output Current Operating Temperature Storage Temperature Symbol VIN, VOUT VCC PD -- TOPE TSTG Value -0.5 to +7.0 -0.5 to +7.0 1.0 50 0 to 70 -55 to +125 Unit V V W mA C C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs* Notes *1 *1 *1 Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -3.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 Unit V V V 0C to + 70C Ambient Operating Temp * : Undershoots of up to -2.0 volts with a pulse width not exceeding 20 ns are acceptable. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. s CAPACITANCE (TA = 25C, f = 1 MHz) Parameter Input Capacitance, A0 to A10 Input Capacitance, RAS, CAS, WE, OE Input/Output Capacitance, DQ1 to DQ8 Symbol CIN1 CIN2 CDQ Max. 5 5 7 Unit pF pF pF 7 To Top / Lineup / Index MB8117800A-60/-70 s DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Note 3 Parameter Notes Symbol VOH VOL II(L) Condition IOH = -5.0 mA IOL = +4.2 mA 0 V VIN VCC; 4.5 V VCC 5.5 V; VSS = 0 V; All other pins not under test = 0 V 0 V VOUT VCC; Data out disabled RAS & CAS cycling; tRC = min RAS = CAS = VIH ICC2 CMOS level RAS = CAS VCC - 0.2 V CAS = VIH, RAS cycling; tRC = min -- -- 1.0 130 -- -- 120 120 -- -- 110 120 -- -- 110 A mA mA mA Values Min. 2.4 -- -10 Typ. -- -- -- Max. -- 0.4 10 A -10 -- 10 130 -- -- 120 2.0 mA mA Unit V Output high voltage Output low voltage Input leakage current (any input) Output leakage current Operating current (Average power supply current) Standby current (Power supply current) MB8117800A-60 IDQ(L) ICC1 *2 MB8117800A-70 TTL level MB8117800A-60 Refresh current #1 (Average power supply current) *2 MB8117800A-70 Fast Page Mode Current Refresh current #2 (Average power supply current) Refresh current #3 (Average power supply current) MB8117800A-60 *2 ICC3 ICC4 MB8117800A-70 MB8117800A-60 ICC5 RAS = VIL, CAS cycling; tPC = min RAS cycling; CAS-before-RAS; tRC = min RAS = VIL, CAS = VIL Self refresh; tRASS = min *2 MB8117800A-70 MB8117800A-60 ICC9 MB8117800A-70 -- -- 1000 8 To Top / Lineup / Index MB8117800A-60/-70 s AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Parameter Time Between Refresh Random Read/Write Cycle Time Read-Modify-Write Cycle Time Access Time from RAS Access Time from CAS Column Address Access Time Output Hold Time Output Buffer Turn On Delay Time Output Buffer Turn Off Delay Time Transition Time RAS Precharge Time RAS Pulse Width RAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time CAS Pulse Width CAS Hold Time CAS Precharge Time (Normal) Row Address Set Up Time Row Address Hold Time Column Address Set Up Time Column Address Hold Time Column Address Hold Time from RAS RAS to Column Address Delay Time Column Address to RAS Lead Time Column Address to CAS Lead Time Read Command Set Up Time Read Command Hold Time Referenced to RAS Read Command Hold Time Referenced to CAS Write Command Set Up Time *14 *14 *15, 20 *13 *19 *11, 12 *10 *6, 9 *7, 9 *8, 9 Notes Symbol tREF tRC tRWC tRAC tCAC tAA tOH tON tOFF tT tRP tRAS tRSH tCRP tRCD tCAS tCSH tCPN tASR tRAH tASC tCAH tAR tRAD tRAL tCAL tRCS tRRH tRCH tWCS MB8117800A-60 Min. -- 110 150 -- -- -- 3 0 -- 3 40 60 15 5 20 15 60 10 0 10 0 15 35 15 30 30 0 0 0 0 Max. 32.8 -- -- 60 15 30 -- -- 15 50 -- 100000 -- -- 45 -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- MB8117800A-70 Min. -- 130 174 -- -- -- 3 0 -- 3 50 70 17 5 20 17 70 10 0 10 0 15 35 15 35 35 0 0 0 0 Max. 32.8 -- -- 70 17 35 -- -- 17 50 -- 100000 -- -- 53 -- -- -- -- -- -- -- -- 35 -- -- -- -- -- -- ns ns ns ns ns ns ns Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 To Top / Lineup / Index MB8117800A-60/-70 (Continued) No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 60 61 62 63 64 65 66 Parameter Write Command Hold Time Write Hold Time from RAS WE Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time DIN Setup Time DIN Hold Time Data Hold Time from RAS RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Lead Time RAS Precharge Time to CAS Active Time (Refresh cycles) CAS Setup Time for CAS -before- RAS Refresh CAS Hold Time for CAS -before- RAS Refresh Access Time from OE Output Buffer Turn Off Delay from OE OE to RAS Lead Time for Valid Data OE Hold Time Referenced to WE OE to Data In Delay Time CAS to Data In Delay Time DIN to CAS Delay Time DIN to OE Delay Time Fast Page Mode RAS Pulse width Fast Page Mode Read/Write Cycle Time Fast Page Mode Read-Modify-Write Cycle Time Access Time from CAS Precharge Fast Page Mode CAS Precharge Time Fast Page Mode RAS Hold Time from CAS Precharge Fast Page Mode CAS Precharge to WE Delay Time *9, 18 *17 *17 *16 *9 *10 *20 *20 *20 Notes Symbol tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tCWD tAWD tRPC tCSR tCHR tOEA tOEZ tOEL tOEH tOED tCDD tDZC tDZO tRASP tPC tPRWC tCPA tCP tRHCP tCPWD MB8117800A-60 Min. 15 35 15 15 15 0 15 35 80 35 50 5 0 10 -- -- 10 5 15 15 0 0 -- 40 80 -- 10 35 55 -- -- -- -- -- -- 15 15 -- -- -- -- -- -- 100000 -- -- 35 -- -- -- Max. -- -- -- -- -- -- -- MB8117800A-70 Min. 15 35 15 17 17 0 15 35 92 39 57 5 0 12 -- -- 10 5 17 17 0 0 -- 45 89 -- 10 40 62 -- -- -- -- -- -- 17 17 -- -- -- -- -- -- 100000 -- -- 40 -- -- -- Max. -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 To Top / Lineup / Index MB8117800A-60/-70 Notes: *1. Referenced to VSS. *2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL, CAS = VIH and VIL > -0.3 V. ICC1, ICC3, ICC4 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC2 is specified during RAS = VIH and VIL > -0.3 V. *3. An initial pause (RAS = CAS = VIH) of 200 s is required after power-up followed by any eight RAS-only cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. *4. AC characteristics assume tT = 5 ns. *5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also transition times are measured between VIH (min) and VIL (max). *6. Assumes that tRCD tRCD (max), tRAD tRAD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig.2 and 3. *7. If tRCD tRCD (max), tRAD tRAD (max), and tASC tAA - tCAC - tT, access time is tCAC. *8. If tRAD tRAD (max) and tASC tAA - tCAC - tT, access time is tAA. *9. Measured with a load equivalent to two TTL loads and 100 pF. *10. tOFF and tOEZ is specified that output buffer change to high impedance state. *11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tAA. *12. tRCD (min) = tRAH (min) + 2 tT + tASC (min). *13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by tCAC or tAA. *14. Either tRRH or tRCH must be satisfied for a read cycle. *15. tWCS is specified as a reference point only. If tWCS tWCS (min) the data output pin will remain High-Z state through entire cycle. *16. Assumes that tWCS < tWCS (min). *17. Either tDZC or tDZO must be satisfied. *18. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H"). Therefore, if tCP is long, tCPA is longer than tCPA (max). *19. Assumes that CAS-before-RAS refresh. *20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristic only. If tWCS tWCS (min), the cycle is an early write cycle and DOUT pin will maintain high impedance state through-out the entire cycle. If tCWD tCWD (min), tRWD tRWD (min), tAWD tAWD (min) and tCPWD tCPWD (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the DOUT pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the DOUT pin, and write operation can be executed by satisfying tRWL, tCWL, and tRAL specifications. 11 To Top / Lineup / Index MB8117800A-60/-70 Fig. 2 - tRAC vs. tRCD tRAC (ns) Fig. 3 - tRAC vs. tRAD tRAC (ns) Fig. 4 - tCPA vs. tCP tCPA (ns) 120 100 80 60 40 90 80 70 60 50 70ns version 60ns version 70 60 50 70ns version 70ns version 60ns version 40 60ns version 30 0 20 40 60 80 100 tRCD (ns) 0 20 30 40 50 60 tRAD (ns) 0 10 20 30 40 50 tCP (ns) 12 To Top / Lineup / Index MB8117800A-60/-70 Fig. 5 - READ CYCLE tRC tRAS RAS VIH VIL tCRP tRCD CAS VIH VIL tAR tCSH tRSH tCAS tRAD tRAL tCAL tASC tCAH tOEL tRP tCDD tASR VIH VIL tRAH A0 to A10 ROW ADD COLUMN ADD tRCS WE VIH VIL tRAC VOH DQ (Output) VOL HIGH-Z tRRH tRCH tAA tCAC tOFF tOH tDZC DQ (Input) VIH VIL HIGH-Z tON tOEA tOEZ tOH tDZO tON tOED OE VIH VIL "H" or "L" DESCRIPTION To implement a read operation, a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level and OE set to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS(tRAC), CAS(tCAC), OE(tOEA) or column addresses (tAA) under the following conditions: If tRCD > tRCD (max), access time = tCAC. If tRAD > tRAD (max), access time = tAA. If OE is brought Low after tRAC, tCAC, or tAA(whichever occurs later), access time = tOEA. However, if either CAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied. 13 To Top / Lineup / Index MB8117800A-60/-70 Fig. 6 - EARLY WRITE CYCLE (OE = "H" or "L") tRC tRAS RAS VIH VIL tCRP tRCD VIH VIL tAR tASR VIH VIL tRAH tASC tCAH tCSH tRSH tCAS tRP CAS A0 to A10 ROW ADD COLUMN ADD tWCR tWCS WE VIH VIL tDHR tDS DQ (Input) VIH VIL tDH tWCH VALID DATA IN VOH DQ (Output) VOL HIGH-Z "H" or "L" DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is an "H" or "L" signal. A write cycle can be implemented in either of three ways - early write, delayed write or read-modify-write. During all write cycles, timing parameters tRWL, tCWL, and tRAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pin is latched with the falling edge of CAS and written into memory. 14 To Top / Lineup / Index MB8117800A-60/-70 Fig. 7 - DELAYED WRITE CYCLE tRC tRAS RAS VIH VIL tAR tRP tCAS tRSH CAS VIH VIL tASR tRAH tASC tCAH tCSH tCRP tRCD A0 to A10 VIH VIL COL ADD COL ADD tRCS tWCH tWP WE VIH VIL tDS tDZC DQ (Input) VIH VIL HIGH-Z tCWL tRWL tDH VALID DATA IN tOED tON VOH DQ (Output) VOL HIGH-Z HIGH-Z tDZO VIH VIL tON tOEZ tOEH OE "H" or "L" Invalid Data DESCRIPTION In the delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins is latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tDS). 15 To Top / Lineup / Index MB8117800A-60/-70 Fig. 8 - READ-MODIFY-WRITE CYCLE tRWC tRAS RAS VIH VIL tCRP CAS VIH VIL tASR VIH VIL tRAH tAR tRP tRCD tRAD tASC tCAH COL ADD A0 to A10 ROW ADD tRWD tRCS VIH VIL tDS tDZC DQ (Input) VIH VIL tCAC tAA VALID tAWD tCWD tCWL tRWL WE tWP tDH VALID DATA IN tOED tRAC VOH DQ (Output) VOL HIGH-Z HIGH-Z tDZO VIH VIL tON tOEA tON tOEZ tOEH OE tOH "H" or "L" DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read-modifywrite cycle, OE must be changed from Low to High after the memory access time. 16 To Top / Lineup / Index MB8117800A-60/-70 Fig. 9 - FAST PAGE MODE READ CYCLE tRASP tRCD RAS VIH VIL tRAD tCRP CAS VIH VIL tASR tRAH VIH VIL tASC tCAH A0 to A10 ROW ADD COL ADD COL ADD COL ADD tRHCP tCSH tCAS tCP tPC tCAS tCAS tRSH tRP tAR tCAH tASC tCAH tASC tRAL tRRH tRCS WE VIH VIL tDZC DQ (Input) VIH VIL tDZO tRCH tRCS tRCH tRCS tRCH tOEL tCPA tDZC HIGH-Z tDZC tCDD HIGH-Z tOH tCAC tOFF tDZO tOH tCAC tDZO tOFF DQ VOH (Output) VOL tON tRAC HIGH-Z tON tAA tOEZ tOEA OE VIH VIL tAA tOEA tOEZ tOED tOH tOH tOED "H" or " L" Valid Data DESCRIPTION The fast page mode of operation permits faster sucessive memory operations at multiple column locations of the same row address. This operations is performed by strobing in the row address and maintaining RAS at a Low level and WE at a Hight level druing all successive memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 17 To Top / Lineup / Index MB8117800A-60/-70 Fig. 10 - FAST PAGE MODE EARLY WRITE CYCLE (OE = "H" or "L") tRASP RAS VIH VIL tCRP tRCD CAS VIH VIL tAR tRAH tASR VIH A0 to A10 VIL ROW ADD tCSH tCAS tCP tPC tCAS tRSH tCAS tRP tCAH tASC COL ADD tCAH tASC tASC tCAH COL ADD COL ADD tWCR tWCS WE VIH VIL tDHR tDS DQ (Input) VIH VIL VALID DATA tWCH tWCS tWCH tWCS tWCH tDH tDS tDH tDS tDH VALID DATA VALID DATA DQ VOH (Output) VOL HIGH-Z "H" or " L" DESCRIPTION The fast page mode early write cycle is executed in the same manner as the fast page mode read cycle except the states of WE and OE are reversed. Data appearing on the DQ pins is latched on the falling edge of CAS and written into memory. During the fast page mode early write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied. 18 To Top / Lineup / Index MB8117800A-60/-70 Fig. 11 - FAST PAGE MODE DELAYED WRITE CYCLE RAS VIH VIL tCSH tCPR tRCD tRASP tPC tCAS tCP tASC tRSH tCAS tCAH COL ADD tRP CAS VIH VIL tASR tRAH ROW ADD tAR tASC COL ADD tCAH tCWL A0 to A10 VIH VIL tRCS WE VIH VIL tDS tDZC DQ (Input) VIH VIL tOED tON DQ VOH (Output) VOL tDZO OE VIH VIL tON tWCH tWP tCWL tWCH tDS tDH tRWL tWP tDH VALID VALID tOEH tON tOED tON tOEZ tOEH tOEZ "H" or " L" Valid Data DESCRIPTION The fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the fast page mode delayed write cycle, OE must me changed from Low to High before WE goes Low (tOED + tT + tDS). 19 To Top / Lineup / Index MB8117800A-60/-70 Fig. 12 - FAST PAGE MODE READ-MODIFY-WRITE CYCLE RAS VIH VIL tCRP tRCD tCWD tRAD tRAH tASR tASC tCAH COL ADD tRASP tRWL tRPWC tCP tASC tCWD tCAH COL ADD tRP CAS VIH VIL A0 to A10 VIH VIL ROW ADD tAWD tRCS WE VIH VIL tRWD tDZC DQ (Input) VIH VIL tDS tCPWD tWCL tWP tRCS tWP tDS tDH VALID VALID tWCL tDH tOED tOED tAA tON HIGH-Z tCAC tON tAA tON tCAC DQ VOH (Output) VOL tON tRAS tDZO tOEZ tOEH tOEA tOEZ tOEH OE VIH VIL tOEA tCPA "H" or " L" Valid Data DESCRIPTION During the fast page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data appears at the DQ pins during a normal cycle. 20 To Top / Lineup / Index MB8117800A-60/-70 Fig. 13 - RAS-ONLY REFRESH (WE = OE = "H" or "L") tRC RAS VIH VIL tASR VIH A0 to A10 VIL tRAH tRAS tRP tRPC ROW ADDRESS tCRP CAS VIH VIL tOFF tOH VOH DQ (Output) VOL DESCRIPTION HIGH-Z tCRP "H" or "L" Referesh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DOUT pins are kept in a high-impedance state. Fig. 14 - CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = "H" or "L") tRC RAS VIH VIL tCPN VIH VIL tCSR tCHR tRAS tRPC tRP CAS tOFF tOH VOH DQ (Output) VOL HIGH-Z "H" or "L" DESCRIPTION CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operating automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. 21 To Top / Lineup / Index MB8117800A-60/-70 Fig. 15 - HIDDEN REFRESH CYCLE tRC tRAS RAS VIH VIL tRCD tRAD CAS VIH VIL tASR tASC tAR A0 to A10 VIH VIL ROW ADDRESS COLUMN ADDRESS tRC tRP tRAS tOEL tRP tCRP tCHR tRSH tRAH tRAL tCAH tRCS WE VIH VIL tRRH tAA tRAC tDZC tCAC HIGH-Z tCDD DQ (Input) VIH VIL tON tOFF tOH VALID DATA OUT VOH DQ (Output) VOL HIGH-Z tDZO OE VIH VIL tOEA tOEZ tOED "H" or "L" DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability. 22 To Top / Lineup / Index MB8117800A-60/-70 Fig. 16 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE RAS VIH VIL tRCD CAS VIH VIL tCRP tCP tFRSH tFCAS tRP VIH A0 to A10 VIL VIH VIL VIH VIL tASC tFCAH COLUMN ADDRESSES tRCS tDZC tFCWD tCWL tRWL tWP tDH VALID DATA IN WE tDS DQ (Input) HIGH-Z tOED tFCAC HIGH-Z HIGH-Z VOH DQ (Output) VOL VIH VIL tDZO tON tOEA tOEH tOEZ OE "H" or "L" Valid Data DESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function of CAS-before-RAS refresh circuitry. If, a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits A0 through A10 are defined by the on-chip refresh counter. Column Address: Bits A0 through A9 are defined by latching levels on A0-A9 at the second falling edge of CAS. The CAS-before-RAS Counter Test procedure is as follows ; 1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles. 2) Use the same column address throughout the test. 3) Write "0" to all 2048 row addresses at the same column address by using normal write cycles. 4) Read "0" written in procedure 3) and check; simultaneously write "1" to the same addresses by using CASbefore-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses generated by the internal refresh address counter. 5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. 90 91 92 93 94 Parameter Access Time from CAS Column Address Hold Time CAS to WE Delay Time CAS Pulse Width RAS Hold Time Symbol tFCAC tFCAH tFCWD tFCAS tFRSH MB817800A-60 Min. Max. -- 50 35 70 90 90 -- -- -- -- MB817800A-70 Min. Max. -- 55 35 77 99 99 -- -- -- -- Unit ns ns ns ns ns Note: Assumes that CAS-before-RAS refresh counter test cycle only. 23 To Top / Lineup / Index MB8117800A-60/-70 Fig. 17 - SELF REFRESH CYCLE (A0-A10 = WE = OE = "H" or "L") RAS VIH VIL tCPN tCSR tRASS tRPS tRPC tCHS CAS VIH VIL tOFF tOH VOH DQ (Output) VOL HIGH-Z "H" or "L" A0 to A10, WE, OE = "H" or "L" (At recommended operating conditions unless otherwise noted.) No. 100 101 102 Parameter RAS Pulse Width RAS Precharge Time CAS Hold Time Symbol tRASS tRPS tCHS MB817800A-60 Min. Max. -- 100 110 -50 -- -- MB817800A-70 Min. Max. 100 -- 125 -50 -- -- Unit s ns ns Note: Assumes self refresh cycle only DESCRIPTION The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator. If CAS goes to "L" before RAS goes to "L" (CBR) and the condition of CAS "L" and RAS "L" is kept for term of tRASS (more than 100 s), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during "RAS = L" and "CAS = L". Exit from self refresh cycle is performed by togging RAS and CAS to "H" with specified tCHS min.. In this time, RAS must be kept "H" with specified tRPS min.. Using self refresh mode, data can be retained without external CAS signal during system is in standby. Restriction for Self Refresh operation; For self refresh operation, the notice below must be considered. 1) In the case that distributed CBR refresh are operated between read/write cycles Self refresh cycles can be executed without special rule if 2,048 cycles of distributed CBR refresh are executed within tREF max.. 2) In the case that burst CBR refresh or distributed burst RAS-only refresh are operated between read/write cycles 2,048 times of burst CBR refresh or 2,048 times of burst RAS-only refresh must be executed before and after Self refresh cycles. Read/Write operation Self Refresh operation Read/Write operation RAS VIH VIL tNS < 2 ms 2,048 burst refresh cycle tRASS tSN < 2 ms * 2,048 burst refresh cycle * * read/write operation can be performed non refresh time within tNS or tSN 24 To Top / Lineup / Index MB8117800A-60/-70 s PACKAGE DIMENSIONS (Suffix: -PJ) 28-pin plastic SOJ (LCC-28P-M07) 3.40 -0.20 +.014 .134 -.008 * 18.420.13(.725.005) 2.75(.108)NOM 0.64(.025)MIN R0.81(.032)TYP +0.35 28 15 10.16 (.400) 10.970.13 (.432.005) NOM INDEX 9.400.51 (.370.020) LEAD No 1 1.270.13 (.050.005) 16.51(.650)REF 14 0.20 -0.02 +.002 .008 -.001 Details of "A" part 2.50(.098)NOM 0.81(.032)MAX +0.05 0.10(.004) "A" 0.430.10(.017.004) C 1995 FUJITSU LIMITED C28058S-2C-1 Dimensions in inches (mm) 25 To Top / Lineup / Index MB8117800A-60/-70 (Continued) (Suffix: -PFTN) 28-pin plastic TSOP (II) (FPT-28P-M14) 28 15 Details of "A" part 0.15(.006) 0.25(.010) 0.15(.006) MAX 0.50(.020) MAX INDEX LEAD No. 1 "A" 14 * 18.410.10 (.725.004) 0.400.10 (.016.004) 0.21(.008) M 11.760.20 (.463.008) 1.150.05(.045.002) 10.160.10 (.400.004) 0.1250.05 (.005.002) 1.27(.050) TYP. 0.10(.004) 0.500.10 (.020.004) 0.05(.002)MIN (STAND OFF) 10.760.20 (.424.008) 16.51(.650) REF. C 1994 FUJITSU LIMITED F28040S-2C-1 Dimensions in inches (mm) 26 To Top / Lineup / Index MB8117800A-60/-70 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9801 (c) FUJITSU LIMITED Printed in Japan 27 |
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